This commit is contained in:
2025-07-11 19:37:26 +09:00
parent dc7e685fb1
commit 7d0f52e616

View File

@@ -375,14 +375,11 @@ if settings.startup['PHI-MI'].value or (settings.startup['PHI-GM'].value and set
circuit_oc.set_slot(1, {value = {type = 'virtual', name = 'signal-RA', quality = 'normal'}, min = (((val % 2) >= 1) and 1 or 0)})
else
for _, s in pairs(circuit_oc.get_signals(defines.wire_connector_id.circuit_red, defines.wire_connector_id.circuit_green)) do
local raw_name = s.name:gsub('^signal%-', '')
if technology_signal[raw_name] then
storage.phi_cl.combinator.research_queue_set[technology_signal[raw_name]] = s.count
for _, cs in pairs(circuit_oc.get_signals(defines.wire_connector_id.circuit_red, defines.wire_connector_id.circuit_green)) do
if cs.signal and cs.signal.type == 'virtual' and technology_signal[cs.signal.name] then
storage.phi_cl.combinator.research_queue_set[cs.signal.name] = ((storage.phi_cl.combinator.research_queue[cs.signal.name] and storage.phi_cl.combinator.research_queue[cs.signal.name]) or 0) + cs.signal.count
end
end
table.insert(storage.phi_cl.combinator.research_queue_set, technology_signal[raw_name])
end
end
end