This commit is contained in:
2025-07-12 01:33:57 +09:00
parent 174f111b97
commit 20c5425c47

View File

@@ -383,11 +383,15 @@ if settings.startup['PHI-MI'].value or (settings.startup['PHI-GM'].value and set
circuit_oc.set_slot(1, {value = {type = 'virtual', name = 'signal-RA', quality = 'normal'}, min = (((val % 2) >= 1) and 1 or 0)})
else
for _, cs in pairs(circuit_oc.get_signals(defines.wire_connector_id.circuit_red, defines.wire_connector_id.circuit_green)) do
if cs.signal and cs.signal.type == 'virtual' and technology_signal[cs.signal.name] then
for i = 1, 7 do
if cs.signal.count % (2 ^ i) == 1 then
storage.phi_cl.combinator.research_queue_set[inserter_direction_reversed] = cs.signal.name
local ls = sc.get_signals(defines.wire_connector_id.circuit_red, defines.wire_connector_id.circuit_green)
if ls and #ls > 0 then
for _, cs in pairs(ls) do
if cs.signal and cs.signal.type == 'virtual' and technology_signal[cs.signal.name] then
for i = 1, 7 do
if cs.count % (2 ^ i) == 1 then
storage.phi_cl.combinator.research_queue_set[inserter_direction_reversed] = cs.signal.name
end
end
end
end